FPGA Implementation of TinyJAMBU Lightweight Cryptographic Engine

This project involved the implementation of the TinyJAMBU lightweight cryptographic algorithm on an FPGA platform using Verilog Hardware Description Language (HDL). The objective was to design and verify a hardware-based encryption engine capable of performing secure data encryption while maintaining efficiency in terms of hardware resources and performance.

The development process required studying the TinyJAMBU cryptographic specification, translating the encryption logic into Verilog modules, and creating a complete verification environment using ModelSim. Instead of relying solely on waveform-based verification methods, comprehensive testbenches were developed to automate testing and validate encryption outputs against expected results.

The project provided hands-on experience in FPGA development, digital circuit design, simulation-driven verification, and hardware security concepts. Significant effort was dedicated to debugging timing issues, validating state transitions, and ensuring correct encryption functionality under various test conditions.

Beyond delivering a working cryptographic solution, the project became a foundation for future digital design work, particularly in processor architecture and custom hardware development. The skills acquired in Verilog design, modular hardware construction, and simulation workflows later proved invaluable when developing more advanced FPGA-based systems.

Initial learning curve with Verilog HDL and FPGA development, understanding the complex TinyJAMBU algorithm, and transitioning from basic waveform inspection to comprehensive, automated simulation-driven verification.

I conducted intensive self-learning on Verilog HDL and FPGA workflows. I translated the cryptographic operations into structured, modular Verilog components and developed dedicated test benches to automate validation, ensuring reliable hardware implementation through a simulation-first development approach.